1. Field of Invention
The invention relates to a method for pattern etching a multi-layer mask.
2. Description of Related Art
Typically, during fabrication of integrated circuits (ICs), semiconductor production equipment utilize a (dry) plasma etch process to remove or etch material along fine lines or within vias or contacts patterned on a semiconductor substrate. The success of the plasma etch process requires an etch chemistry including chemical reactants suitable for selectively etching one material while substantially not etching another material.
For example, on a semiconductor substrate, a pattern formed in a multi-layer mask can be transferred to an underlying layer of a selected material utilizing a plasma etching process. The multi-layer mask may include a lithographic layer, such as a photo-resist layer, having a pattern formed therein using a lithographic process. The multi-layer mask may further include one or more additional mask layers underlying the lithographic layer, such as an anti-reflective coating (ARC), an organic planarization layer (OPL), an organic dielectric layer (ODL), etc., wherein the pattern formed in the lithographic layer is subsequently transferred to the one or more additional mask layers via a sequence of etching steps.
During the transfer of the pattern from the lithographic layer to the one or more additional mask layers, it is desirable to control the critical dimension (CD) of the pattern, as well as maintain and/or improve the pattern integrity (e.g., line edge roughness (LER), line width roughness (LWR), etc.). Additionally, it is desirable to controllably achieve a uniform distribution of the CD/pattern integrity across the substrate. Furthermore, it is desirable to controllably achieve the same CD/pattern integrity for both nested (closely spaced) structures and isolated (widely spaced) structures. While etch chemistries exist for trimming CD, there still exists the need for an etch process capable of both adding and subtracting CD when patterning a multi-layer mask.